The present invention relates to field-effect transistors (FETs), and more particularly to thin-body fully-depleted semiconductor-on-insulator (SOI) FETs including a back gate self-aligned to a front gate, and methods of manufacturing the same.
Complementary metal-oxide semiconductor (CMOS) field-effect transistors (FETs) are employed in almost every electronic circuit application, such as signal processing, computing, and wireless communications. Scaling down the gate length of both N-channel FETs (NFETs) and P-channel FETs (PFETs) in CMOS circuits to shorter dimensions can increase the speed of the CMOS circuits. However, detrimental short-channel effects can lead to high off-state leakage currents in CMOS devices, thereby increasing the power consumption. In case of extreme short-channel effects, CMOS circuits fail to operate.
Fully-depleted semiconductor-on-insulator (FDSOI) FETs with thin SOI bodies provide improved electrostatic integrity than thick-body partially-depleted SOI (PDSOI) FETs. For example, K. K. Young, “Short-channel effect in fully-depleted SOI MOSFETs”, IEEE Trans. Electron Devices, vol. 36, pp. 399-402 (1989); V. P. Trivedi and J. G. Fossum, “Scaling fully depleted SOI CMOS”, IEEE Trans. Electron Devices, vol. 50, pp. 2095-2103 (2003); A. Kumar, J. Kedzierski, and S. E. Laux, “Quantum-based simulation analysis of scaling in ultrathin body device structures”, IEEE Trans. Electron Devices, vol. 52, pp. 614-617 (2005); and D. V. Singh et al., “Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25 nm gate lengths”, in IEDM Tech. Dig., 2005, pp. 511-514 provide theoretical predictions and experimental demonstration of superior short-channel characteristics of thin semiconductor-on-insulator (SOI) FETs.
As described in V. P. Trivedi and J. G. Fossum, “Nanoscale FDSOI CMOS: thick or thin BOX ?”, IEEE Electron Device Lett., vol. 26-28, pp. 26,2005, the application of a back gate voltage with the buried oxide (BOX) acting as the back gate dielectric leads to further improvement in short-channel effects of thin SOI FETs. Further, it is well known that a back gate voltage can also be used for tuning the FET threshold voltage.
Several back-gated SOI structures have been proposed in the past, though primarily for threshold voltage control, where the back gate electrode is beneath the entire active area, such as, in U.S. Pat. No. 5,289,027 to Terrill et al., U.S. Pat. No. 5,619,054 to Hashimoto, U.S. Pat. No. 6,080,610 to Hashimoto, and U.S. Pat. No. 6,307,233 Awaka et al. The overlap of the back gate electrode with the source/drain region leads to increased parasitic capacitance, which leads to slower FET switching speed. Therefore, in order to minimize the parasitic capacitance penalty, localized back gates are desired.
A known method for creating localized and self-aligned back gates is a replacement gate process, where the back gates are implanted after the removal of the dummy gate. This method is disclosed, for example, in U. S. Pat. No. 5,942,781 to Burr et al., U.S. Pat. No. 6,072,217 to Burr, U.S. Pat. No. 6,100,567 to Burr, U.S. Pat. No. 6,383,904 to Yu, U.S. Pat. No. 6,391,695 to Yu, U.S. Pat. No. 6,423,599 to Yu, and U.S. Pat. No. 6,611,023 to En et al. Creating a back gate in a replacement gate flow involves back gate ion implantation through the SOI channel and the BOX layers, which necessitates the use of high energy ion implantation. High energy implants through the thin SOI region may amorphize the channel region, which is detrimental for FET drive current. Furthermore, high energy back gate implants will have large vertical as well as lateral straggle (e.g., 300 nm for As implantation at 500 keV of energy). Large lateral straggle not only limits the proximity of adjacent NFETs and PFETs, but also leads to unintentional overlap of the back gate electrode with the source/drain region.
In general, reliable alignment of forming FDSOI devices in which a back gate is aligned to a front gate poses a challenge to semiconductor manufacturing. An economical and manufacturing-friendly method of reliably aligning a back gate to a front gate on FDSOI devices while minimizing an overlay offset is desirable.